1. Field of the Invention
The present invention relates to an on-chip electrostatic discharge protection device, which is provided on a chip and protects an internal circuit against electrostatic discharge.
2. Description of the Related Art
The recent complex and high density design of semiconductor devices is bringing about such a problem that semiconductor devices are damaged by electrostatic discharge (ESD) during an assembling process or the like in the fabrication process. As one measure against the problem, an on-chip electrostatic discharge protection device (hereinafter also called xe2x80x9cESD protection devicexe2x80x9d), which protects elements in an internal circuit by efficiently discharging an electrostatic discharge current in a safe path, is provided in the chip of a semiconductor device.
Conventionally, a protection device comprised of a protection resistor and a diode has been used as an ESD protection device for a circuit device, such as CMOSLSI. However, the use of ESD protection devices that utilize the snap-back phenomenon of an MOSFET (Metal Oxide Semiconductor Field Effect Transistor), which has a lower resistance and a better voltage clamping performance, is gradually becoming popular.
In an ESD protection device comprised of an MOSFET, as a large current is input to the drain of the MOSFET, the PN junction on the drain side causes avalanche breakdown, so that the current flows toward the substrate and is absorbed by, for example, the ground contact, such as a latch-up preventing P+ guard ring. A potential difference occurs along the current path in accordance with the product of the resistance of the path and the current value, thereby increasing the local potential of the substrate. As a result, the potential of the PN junction on the source side increases to cause conduction, thereby further increasing the current that flows toward the substrate. Positive feedback occurs on the current that flows toward the substrate, so that the PN junction on the source side is forward-biased spontaneously, i.e., within a time of less than one nano second and comes to the operational state of a parasitic bipolar. This forms a low-resistance current path.
In such a case of using an MOSFET as an ESD protection device, the entire width of the MOSFET should be set to the order of about several hundred micrometers to ensure a sufficiently low resistance of several ohms in order to demonstrate the adequate protecting performance. Normally, small transistors whose widths are of about 10 to 100 xcexcm (which are called xe2x80x9cfingersxe2x80x9d) are laid out in parallel are used.
Such a MOSFET type ESD protection device however has the following problems. Because the current is apt to concentrate on the drain-side end portion of the MOSFET type ESD protection device, the drain-side end portion of the gate electrode generates heat, so that the MOSFET type ESD protection device is likely to break down. Further, as the timings at which the individual fingers snap back to have a low resistance differ from one another, the current concentrates on the that finger which has snapped back faster so that the finger is likely to break down. Those shortcomings lower the protecting performance of the MOSFET type ESD protection device. Therefore, it is important for the MOSFET type ESD protection device to take some measures to prevent the excess current from flowing to the end portion of the gate electrode and to allow the current to evenly flow in all the fingers in the widthwise direction of the transistor.
An MOSFET has another problem such that it is technically difficult to lower its high holding voltage. To make the fabrication cost for semiconductor devices low, it is necessary to increase (the protecting performance/layout area) ratio of an ESD protection device. However, reducing the layout area increases the resistance of the MOSFET, thereby lowering the protecting performance. There is a limit to reduction in the resistance of an MOSFET per unit area, thereby limiting an improvement on (the protecting performance/layout area) ratio.
In this respect, attention is being paid to an SCR (silicon controlled rectifier) type ESD protection device. The SCR type ESD protection device is described in, for example, U.S. Pat. No. 5,502,317 and IEEE Electron Device Letters, Volume 12, Issue 1, January 1991 p. 21 to 22, entitled xe2x80x9cA low-voltage triggering SCR for on-chip ESD protection at output and input padsxe2x80x9d by Chatterjee, A., Polgreen, T. The SCR type ESD protection device can allow a larger current to flow through it as compared with a protection device which uses an MOSFET.
The SCR-used ESD protection device is composed of an SCR which lets the electrostatic current flow and escape outside and a trigger current supplying circuit (hereinafter also simply called xe2x80x9ctrigger circuitxe2x80x9d) for latching the SCR. When a voltage to be applied to the trigger circuit exceeds a given value, the current starts to flow through the circuit. Various types of trigger circuits including the one that uses an NMOSFET have been devised.
The following will discuss first prior art which is an ESD protection device using a PN diode as the trigger current supplying circuit. FIG. 1 is a plan view showing the ESD protection device according to the first prior art, FIG. 2 is a cross-sectional view along line B-Bxe2x80x2 in FIG. 1 and FIG. 3 is an equivalent circuit diagram of the conventional ESD protection device. As shown in FIGS. 1 to 3, a P+ substrate 101 of P+ silicon is provided in the ESD protection device. An epitaxial layer 102 of Pxe2x88x92 silicon is formed on the P+ substrate 101. An N well 104 is formed in the top surface of the epitaxial layer 102 and a P well 103 is formed in contact with the N well 104 in such a way as to surround the N well 104. A P+ diffusion region 106, an N+ diffusion region 107 and a P+ diffusion region 110 are formed on the top surface of the P well 103 and a P+ diffusion region 108 and an N+ diffusion region 109 are formed on the top surface of the N well 104.
As shown in FIG. 1, the P+ diffusion region 106, the N+ diffusion region 107, the P+ diffusion region 108, the N+ diffusion region 109 and the P+ diffusion region 110 are laid out in line in the named order as seen from the direction that is perpendicular to the surface of the P+ substrate 101. Each diffusion region has a rectangular shape whose lengthwise direction is orthogonal to the layout direction of the individual diffusion regions. That is, the individual diffusion regions are laid out in parallel to one another. The lengths of the individual diffusion regions in the lengthwise direction are equal to one another. Further, a device isolation region 111 is formed in those regions of the top surface of the epitaxial layer 102 which exclude the individual diffusion regions.
As shown in FIGS. 2 and 3, the P+ diffusion region 108, the N well 104 and the P+ substrate 101 form a vertical PNP bipolar transistor 114 and the N well 104, the P well 103 and the N+ diffusion region 107 form a horizontal NPN bipolar transistor 115. The P well 103 is connected to the P+ substrate 101 via the epitaxial layer 102. With this structure, the base (N well 104) of the vertical PNP bipolar transistor 114 and the collector (N well 104) of the horizontal NPN bipolar transistor 115 are common to each other and the emitter (P+ substrate 101) of the vertical PNP bipolar transistor 114 and the base (P well 103) of the horizontal NPN bipolar transistor 115 are connected together. Further, the P+ diffusion region 108, the N well 104, the P well 103 and the N+ diffusion region 107 form a PNPN SCR and the P+ diffusion region 108 serves as the anode of this SCR while the N+ diffusion region 107 serves as the cathode of the SCR.
An input pad 112 is connected to the P+ diffusion region 108 or the anode, the N+ diffusion region 109 which is a well contact and a trigger circuit 113. The trigger circuit 113 is connected to the P+ diffusion region 106 which is a trigger tap. The N+ diffusion region 107 or the cathode is connected to a ground pad 116 and the P+ substrate 101 is also connected to the ground.
In the ESD protection device of the first prior art, when a positive surge current is input to the input pad 112, the trigger circuit 113 goes to an ON state to let the current flow to the P+ diffusion region 106 or the trigger tap. Accordingly, the current flows to a PN diode which is composed of the P well 103 and the N+ diffusion region 107, raising the potential at the bottom of the N+ diffusion region 107. Part of the electron current discharged from the N+ diffusion region 107 flows into the PN diode, while the rest flows into the N well 104 via the horizontal NPN bipolar transistor 115 and is absorbed by the N+ diffusion region 109 or the well contact.
As the current flows in the N well 104 at this time, a potential difference equivalent to the product (Ixc3x97R) of the current value (I) and the resistance (R) is produced in the N well 104, thereby lowering the potential at that portion of the N well 104 which serves as the base of the vertical PNP bipolar transistor 114. This causes the current to flow between the collector (P+ diffusion region 108) and the emitter (P+ substrate 101) of the vertical PNP bipolar transistor 114 and the substrate potential increases as the current is supplied to the P+ substrate 101. As a result, the potential of the P well 103 (the base of the horizontal NPN bipolar transistor 115) connected to the P+ substrate 101 increases so that the horizontal NPN bipolar transistor 115 conducts further. This leads to further conduction of the vertical PNP bipolar transistor 114.
As such a phenomenon occurs, positive feedback occurs in the vertical PNP bipolar transistor 114 and the horizontal NPN bipolar transistor 115, thus forming a low-resistance current path between the anode (P+ diffusion region 108) and the cathode (N+ diffusion region 107). As the turn-on speed of the SCR depends on the distance between the anode and the cathode or the distance between the cathode and the N well, this distance is generally set to the minimum but is set larger in some case to adjust the holding voltage and holding current to high values.
A technique similar to the first prior art is disclosed in, for example, 1995 IEDM, p. 547-550 entitle xe2x80x9cSubstrate Triggering and Salicide Effects on ESD Performance and Protection Circuit Design in Deep Submicron CMOS Processesxe2x80x9d by Ameraskera et al. and Japanese Patent Laid-Open No. 107074/1997. In Japanese Patent Laid-Open No. 107074/1997, an N type MOSFET is used as a circuit which supplies the substrate current and a circuit which connects the source of that MOSFET to a P+ diffusion region is used as a substrate bias circuit.
Another type of ESD protection device as described below has been proposed too. In an SCR type ESD protection device, the internal circuit also operates as an SCR due to ESD, causing a large current to flow in the ESD protection device which in turn may be thermally damaged. In this respect, the first prior art uses a P-on-P+ substrate which has a Pxe2x88x92 epitaxial silicon layer formed on a P+ silicon substrate to a thickness of about 3 to 5 xcexcm. This design makes it hard for the ESD-originated flow of the current into the internal circuit. Accordingly, however, it becomes extremely difficult to trigger the SCR of the protection device. There may be a case of using a high-resistance substrate which has a Pxe2x88x92 epitaxial silicon layer grown on a Pxe2x88x92 silicon substrate. This design makes it easier to trigger the SCR of the protection device at a risk that the SCR of the protection device would be latched up by noise or the like at the time of the normal operation of the semiconductor device. To reduce the risk, an ESD protection device called a high-current trigger SCR whose trigger current to turn on the SCR (thyristor) is intentionally set high has been devised too. This high-current trigger SCR aims at avoiding a risk that the SCR would be latched during the operation of the LSI.
However, the conventional SCR type ESD protection device has the following problems. As the miniaturization of the CMOS-LSIs gain pace so the gate oxide film needs to become thinner. This lowers the breakdown voltage of the gate oxide film so that the gate oxide film is very susceptible to ESD. As reported by J. Wu et al. in xe2x80x9cBreakdown and latent damage of ultra-thin gate oxides under ESD stress conditionsxe2x80x9d, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000, p. 287-295, for example, the conventional system called a low-voltage trigger SCR takes time for the SCR to have a low resistance after it is turned on. This may result in the overshooting of the voltage before the SCR is turned on, in which case the internal circuit may not be protected. With regard to low-resistance epitaxial substrates, in particular, there have been multiple reports that it is extremely difficult to latch SCRs.
In case of an MOSFET type protection device, the micro-fabrication of MOSFETs makes the gate length shorter, so that the protection device is turned on faster. Therefore, the response speed of the protection device does not matter. In case of an SCR type protection device, on the other hand, the turn-on speed depends on the distance between the anode and cathode of the SCR or the length of the current path. To improve the turn-on speed of the SCR, therefore, it is preferable to make the anode-cathode distance as short as possible. In order to secure the margin in the fabrication process and keep the isolation breakdown voltage, however, the SCR type protection device cannot have the anode-cathode distance set shorter than 0.6 to 1.0 xcexcm, which limits the scale of micro-fabrication. This means that there is a limit to an improvement on the turn-on speed made by shortening the anode-cathode distance. Although the ESD protection device of the first prior art has the shortest anode-cathode distance allowable by the fabrication process, the turn-on speed is not sufficient. This is the reason why the response speed of the SCR has become an issue as mentioned in the aforementioned documents.
A device structure which optimizes the position for supplying the trigger current to an SCR in order to make the turn-on speed faster than the first prior art is described in Electrical Overstress/electrostatic Discharge Symposium Proceedings 2001, p. 22-31, xe2x80x9cGGSCRs: GGNMOS triggered Silicon Controlled Rectifiers for ESD Protection in Deep Submicron CMOS Processxe2x80x9d by Christian C. Russ et al. and U.S. patent application Ser. No. 2002/0053704. This ESD protection device will be discussed as second prior art.
FIG. 4 is a plan view showing an SCR type ESD protection device according to the second prior art. Same symbols are given to those structural elements shown in FIG. 4 which are identical to or correspond to the structural elements shown in FIGS. 1 to 3 to avoid repeating their detailed and redundant description. According to the second prior art, as shown in FIG. 4, the N+ diffusion region 107 or the cathode is separated into two between which the P+ diffusion region 106 or the trigger tap is located. The second prior art aims at latching the SCR more quickly by supplying the trigger current directly to the P well 103 or the base of the horizontal bipolar transistor 115. In the second prior art, the distance between the anode and cathode of the SCR is minimized too.
The N well pick-up diffusion in the N well is generally connected to the power supply to make it easier to latch the SCR. Such a protection device will be discussed as third prior art. FIG. 5 is a cross-sectional view of an SCR type ESD protection device according to the third prior art. Same symbols are given to those structural elements shown in FIG. 5 which are identical to or correspond to the structural elements shown in FIGS. 1 to 3 to avoid repeating their detailed and redundant description.
As shown in FIG. 5, the N+ diffusion region 109 or the well contact is connected to a power supply line 117 in the third prior art. This allows the substrate current to flow to the diode that is formed by the P well 103 and the N well 104, thus lowering the potential at that portion of the N well 104 which serves as the base of the vertical bipolar transistor 114. As a result, latching of the SCR becomes easier, thereby improving the protecting performance.
The surest way to prevent the latch-up of the SCR when the device is operating normally is to set the holding current and holding voltage needed to operate the SCR high. In this respect, an SCR called a holding-current controlled SCR has been proposed as described in Electrical Overstress/electrostatic Discharge Symposium Proceedings 2002, p. 10-17 (FIG. 5), xe2x80x9cHigh Holding Current SCRs (HHI-SCR) for ESD protection and Latch-up-Immune IC operationxe2x80x9d by Markus P. J. et al. and U.S. patent application Ser. No. 2002/0153571. The disclosed schemes adjusts the level of the holding current by laying out a protection device in such a way that the N well resistance and/or the substrate resistance becomes lower, connecting an external resistor element of polysilicon to in series to at least one of the substrate resistor and the N well resistor and adjusting the resistance of the external resistor element.
The above-described prior arts have the following problems. While the second prior has an improvement on the position for supplying the trigger current, it has the same problems as the first prior art on the other portions, such as the diffusion regions in the N well. The second prior therefore has an insufficient effect of improving the turn-on speed.
The high-trigger-current SCR and holding-current controlled SCR should be designed to effectively reduce the well resistance in order to secure the noise immunity of the SCR. Like the first and second prior arts, therefore, the high-trigger-current SCR and holding-current controlled SCR suffer the extreme difficulty in triggering and insufficient turn-on speed. The triggering difficulty means that the size of the trigger current supplying device should be made larger, which increases the layout area and the parasitic capacitance.
While the technique of the third prior art is effective to some extent as a protection device for ESD from the input pad, it cannot be applied to ESD from the power supply.
The turn-on speed of the SCR may be increased by adjusting the impurity concentration in the diffusion regions or the like in an ESD protection device. From the viewpoint of the fabrication process, the impurity concentration in the ESD protection device should be set equal to the impurity concentration in the internal circuit as the protection target. That is, from the viewpoint of the fabrication cost for semiconductor devices, it is practically impossible to control parameters, such as the operation speed, by adjusting the impurity concentration in the ESD protection device separately from the impurity concentration in the internal circuit.
Accordingly, it is an object of the invention to provide an electrostatic discharge protection device which has a fast turn-on speed and can be used both as a protection device for an input pad and a protection device for a power supply, and an electrostatic discharge protection device which can increase the trigger current of an SCR so as to have a good noise immunity.
According to the invention, there is provided an electrostatic discharge protection device for protecting an internal circuit against electrostatic discharge applied externally. The electrostatic discharge protection device comprises an input pad connected to outside and the internal circuit; a trigger circuit which is connected to the input pad and in which a current flows when a voltage applied from the input pad exceeds a predetermined value; a first conductivity type semiconductor substrate; a second conductivity type well formed in a surface of the first conductivity type semiconductor substrate; a first first conductivity type diffusion region formed in that region of the surface of the first conductivity type semiconductor substrate which excludes the second conductivity type well and connected to the trigger circuit; a first second conductivity type diffusion region formed apart from both the second conductivity type well and the first first conductivity type diffusion region in the surface of the first conductivity type semiconductor substrate and connected to a reference potential electrode; a second first conductivity type diffusion region formed in a surface of the second conductivity type well and connected to the input pad; and second second conductivity type diffusion region formed in the surface of the second conductivity type well and connected to the input pad. And, a distance between the second first conductivity type diffusion region and the second second conductivity type diffusion region is non-uniform in a first direction orthogonal to a direction extending toward the second second conductivity type diffusion region from the second first conductivity type diffusion region.
According to the invention, the second first conductivity type diffusion region, the second conductivity type well and the first conductivity type semiconductor substrate form a vertical bipolar transistor, and the second conductivity type well, the first conductivity type semiconductor substrate and the first second conductivity type diffusion region form a horizontal bipolar transistor. The second first conductivity type diffusion region, the second conductivity type well, the first conductivity type semiconductor substrate and the first second conductivity type diffusion region form an SCR (thyristor). As electrostatic discharge is input to the input pad, the current flows into the trigger circuit and this current is input to the first first conductivity type diffusion region. Accordingly, the current flows into a diode which is comprised of the first conductivity type semiconductor substrate and the first second conductivity type diffusion region and part of the current discharged from the first second conductivity type diffusion region flows into the second second conductivity type diffusion region in the second conductivity type well via the horizontal bipolar transistor. As the current flows into the second conductivity type well, a potential difference is produced to turn on the vertical bipolar transistor, thereby permitting the current flow. As a result, the potential of the first conductivity type semiconductor substrate changes and the horizontal bipolar transistor conducts further, thus forming a low-resistance current path between the second first conductivity type diffusion region and the first second conductivity type diffusion region.
At this time, because the distance between the second first conductivity type diffusion region and the second second conductivity type diffusion region is not uniform in the first direction at the stage where the vertical bipolar transistor is turned on, the potential difference between the second first conductivity type diffusion region and the second second conductivity type diffusion region becomes greater at that portion of the second first conductivity type diffusion region which has a large distance with respect to the second second conductivity type diffusion region, so that the vertical bipolar transistor becomes easier to be latched there. As a result, the turn-on speed of the SCR is improved. The electrostatic discharge protection device according to the invention can be connected to the input terminal of the internal circuit as well as the power supply terminal, so that the internal circuit can be protected against both electrostatic discharge coming from the input terminal and electrostatic discharge coming from the power supply terminal. As apparent from the above, the invention can improve the turn-on speed of the SCR by properly selecting the shape and layout position of the second second conductivity type diffusion region. This can provide an electrostatic discharge protection device which has a fast turn-on speed and is easily triggered even if the well resistance and the substrate resistance are lowered to improve the noise immunity of the SCR.
It is preferable that the second second conductivity type diffusion region should be formed in such a position as to sandwich the second first conductivity type diffusion region together with the second first conductivity type diffusion region, and a length in the first direction in the second second conductivity type diffusion region should be shorter than a length in the first direction in the second first conductivity type diffusion region. This design can make the distance between the second first conductivity type diffusion region and the second second conductivity type diffusion region is non-uniform without increasing the circuit area.
It is also preferable that one of the first second conductivity type diffusion region and the second second conductivity type diffusion region should have a rectangular shape and at least two sides of that one diffusion region should face the other diffusion region. This design can reduce the resistance between the first second conductivity type diffusion region and the second second conductivity type diffusion region and can thus improve the noise immunity. In general, reducing the resistance between those two regions makes it difficult to turn on the SCR while the noise immunity is improved. The structure of the invention however makes it easier to trigger the SCR.
Further, it is preferable that the second first conductivity type diffusion region should have a main portion located between the first second conductivity type diffusion region and the second second conductivity type diffusion region; and an extending portion extending from the main portion in a direction toward the second second conductivity type diffusion region. This can make the anode larger to increase the substrate current.
Furthermore, it is preferable that the second first conductivity type diffusion region should have a comb-like shape having a proximal end portion extending in the first direction and a plurality of distal end portions extending from the proximal end portion in a second direction orthogonal to the first direction, and the second second conductivity type diffusion region should be located between the distal end portions. This structure can make the area of the second first conductivity type diffusion region larger than the area of the second second conductivity type diffusion region. As a result, the effective well resistance becomes lower and the trigger current becomes greater, making it possible to reduce the risk that the SCR would be latched due to the influence of the substrate noise or the like at the time the LSI operates. Alternatively, it is preferable that the second second conductivity type diffusion region should have a comb-like shape having a proximal end portion extending in the first direction and a plurality of distal end portions extending from the proximal end portion in a second direction orthogonal to the first direction, and the second first conductivity type diffusion region should be located between the distal end portions. Apparently, the invention can reduce the well resistance of the SCR to improve the noise immunity by properly selecting the shapes and layout positions of the second first conductivity type diffusion region and the second second conductivity type diffusion region.
It is also preferable that the first first conductivity type diffusion region, the first second conductivity type diffusion region, the second first conductivity type diffusion region and the second second conductivity type diffusion region should be laid out in a named order. With the design, the current that flows to the second second conductivity type diffusion region from the first second conductivity type diffusion region always passes the second first conductivity type diffusion region or the underlying region, so that the non-uniform potential in the second first conductivity type diffusion region or the underlying region makes it easier to turn on the SCR.
As elaborated above, the invention can make it easier to latch the vertical bipolar transistor and improve the turn-on speed of the SCR by setting the distance between the second first conductivity type diffusion region which is the anode and the second second conductivity type diffusion region which is the well contact non-uniform. It is therefore possible to prove an electrostatic discharge protection device capable of protecting the internal circuit reliably.